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r10ds0151ej0100 rev.1.00 page 1 of 12 2013.6.21 r1lp0108e series 1mb advanced lpsram (128k word x 8bit) description the r1lp0108e series is a family of low voltage 1-mbit static rams organized as 131,072-word by 8-bit, fabricated by renesas?s high-performance 0.15um cmos and tft tech nologies. the r1lp0108e seri es has realized higher density, higher performance and low power consumption. the r1lp0108e series is suitable for memory applications where a simple interfacing, battery operating and battery backup are the important design objectives. it has been packaged in 32-pin sop,32-pin tsop and 32-pin stsop. features ? single 4.5~5.5v power supply ? small stand-by current: 0.6a (5.0v, typical) ? no clocks, no refresh ? all inputs and outputs are ttl compatible. ? easy memory expansion by cs1# and cs2 ? common data i/o ? three-state outputs: or-tie capability ? oe# prevents data contention on the i/o bus r10ds0151ej0100 rev.1.00 2013.6.21
r1lp0108e series r10ds0151ej0100 rev.1.00 page 2 of 12 2013.6.21 ordering information orderable part name access time temperature range package shipping container quantity r1lp0108esn-5sr#b* 55 ns 0 ~ +70c 525-mil 32-pin plastic sop prsp0032df-a (32p2s-a) tube max. 25pcs/tube max. 225pcs/inner bag max. 900pcs/inner box r1lp0108esn-5si#b* -40 ~ +85c r1lp0108esn-7sr#b* 70 ns 0 ~ +70c r1lp0108esn-7si#b* -40 ~ +85c r1lp0108esn-5sr#s* 55 ns 0 ~ +70c embossed tape 1000pcs/reel r1lp0108esn-5si#s* -40 ~ +85c r1lp0108esn-7sr#s* 70 ns 0 ~ +70c r1lp0108esn-7si#s* -40 ~ +85c r1lp0108esa-5sr#b* 55 ns 0 ~ +70c 8mm13.4mm 32-pin plastic stsop (normal-bend type) ptsa0032kb-a (32p3k-b) tray max. 234pcs/tray max. 1872pcs/inner box R1LP0108ESA-5SI#b* -40 ~ +85c r1lp0108esa-7sr#b* 70 ns 0 ~ +70c r1lp0108esa-7si#b* -40 ~ +85c r1lp0108esa-5sr#s* 55 ns 0 ~ +70c embossed tape 1000pcs/reel R1LP0108ESA-5SI#s* -40 ~ +85c r1lp0108esa-7sr#s* 70 ns 0 ~ +70c r1lp0108esa-7si#s* -40 ~ +85c r1lp0108esf-5sr#b* 55 ns 0 ~ +70c 8mm20mm 32-pin plastic tsop (normal-bend type) ptsa0032ka-a (32p3h-e) tray max. 156pcs/tray max. 1248pcs/inner box r1lp0108esf-5si#b* -40 ~ +85c r1lp0108esf-7sr#b* 70 ns 0 ~ +70c r1lp0108esf-7si#b* -40 ~ +85c r1lp0108esf-5sr#s* 55 ns 0 ~ +70c embossed tape 1000pcs/reel r1lp0108esf-5si#s* -40 ~ +85c r1lp0108esf-7sr#s* 70 ns 0 ~ +70c r1lp0108esf-7si#s* -40 ~ +85c
r1lp0108e series r10ds0151ej0100 rev.1.00 page 3 of 12 2013.6.21 pin arrangement nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd v cc a15 cs2 we# a13 a8 a9 a11 oe# a10 cs1# dq7 dq6 dq5 dq4 dq3 32-pin sop 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a11 a9 a8 a13 we# cs2 a15 vcc nc a16 a14 a12 a7 a6 a5 a4 oe# a10 cs1# dq7 dq6 dq5 dq4 dq3 gnd dq2 dq1 dq0 a0 a1 a2 a3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32-pin stsop a11 a9 a8 a13 we# cs2 a15 vcc nc a16 a14 a12 a7 a6 a5 a4 oe# a10 cs1# dq7 dq6 dq5 dq4 dq3 gnd dq2 dq1 dq0 a0 a1 a2 a3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32-pin tsop
r1lp0108e series r10ds0151ej0100 rev.1.00 page 4 of 12 2013.6.21 pin description pin name function vcc power supply vss ground a0 to a16 address input dq0 to dq7 data input/output cs1# chip select 1 cs2 chip select 2 we# write enable oe# output enable nc non connection block diagram a 0 cs1# a 1 we# oe# a 16 dq0 dq1 dq7 vcc vss column decoder dq buffer address buffer row decoder sense / write amplifier clock generator memory array 128k-word x8-bit cs2
r1lp0108e series r10ds0151ej0100 rev.1.00 page 5 of 12 2013.6.21 operation table cs1# cs2 we# oe# dq0~7 operation x l x x high-z stand-by h x x x high-z stand-by l h l x din write l h h l dout read l h h h high-z output disable note 1. h: v ih l:v il x: v ih or v il absolute maximum parameter symbol value unit power supply voltage relative to vss vcc -0.3 to +7 v terminal voltage on any pin relative to vss v t -0.3 *1 to vcc+0.3 *2 v power dissipation p t 0.7 w operation temperature topr *3 r ver. 0 to +70 c i ver. -40 to +85 storage temperature range tstg -65 to 150 c storage temperature range under bias tbias *3 r ver. 0 to +70 c i ver. -40 to +85 note 1. ?3.0v for pulse 30ns (full width at half maximum) 2. maximum voltage is +7v. 3. ambient temperature range depends on r/i-version. please see table on page 1.
r1lp0108e series r10ds0151ej0100 rev.1.00 page 6 of 12 2013.6.21 dc operating conditions parameter symbol min. typ. max. unit note supply voltage vcc 4.5 5.0 5.5 v vss 0 0 0 v input high voltage v ih 2.2 - vcc+0.3 v input low voltage v il -0.3 - 0.8 v 1 ambient temperature range r ver. ta 0 - +70 c 2 i ver. -40 - +85 c 2 note 1. ?3.0v for pulse 30ns (full width at half maximum) 2. ambient temperature range depends on r/i-version. please see table on page 1. dc characteristics parameter symbol min. typ. max. unit test conditions input leakage current | i li | - - 1 ? a vin = vss to vcc output leakage current | i lo | - - 1 ? a cs1# =v ih or cs2 =v il or oe# =v ih , v i/o =vss to vcc average operating current i cc1 - 25 35 ma min. cycle, duty =100%, i i/o = 0ma cs1# =v il , cs2 =v ih , others = v ih /v il i cc2 - 2 5 ma cycle =1 ? s, duty =100%, i i/o = 0ma cs1# 0.2v, cs2 vcc-0.2v, v ih vcc-0.2v, v il 0.2v standby current i sb - - 3 ma ?cs2 =v il ? or ?cs2 = v ih and cs1# =v ih ?, others = vss to vcc standby current i sb1 - 0.6 *1 2 ? a ~+25c vin = vss to vcc (1) cs2 0.2 or (2) cs1# vcc-0.2v, cs2 vcc-0.2v - - 3 ? a ~+40c - - 8 ? a ~+70c - - 10 ? a ~+85c output high voltage v oh 2.4 - - v i oh = -1ma v oh2 vcc - 0.5 - - v i oh = -0.1ma output low voltage v ol - - 0.4 v i ol = 2ma note 1. typical parameter indicates the value for the center of distribution at 5.0v (t a= 25oc), and not 100% tested. capacitance (vcc = 4.5v ~ 5.5v, f = 1mhz, ta = 0 ~ +70c / -40 ~ +85c *2 ) parameter symbol min. typ. max. unit test conditions note input capacitance c in - - 8 pf vin =0v 1 input / output capacitance c i/o - - 10 pf v i/o =0v 1 note 1. this parameter is sampled and not 100% tested. 2. ambient temperature range depends on r/i-version. please see table on page 1.
r1lp0108e series r10ds0151ej0100 rev.1.00 page 7 of 12 2013.6.21 ac characteristics test conditions (vcc = 4.5v ~ 5.5v, ta = 0 ~ +70c / -40 ~ +85c *1 ) ? input pulse levels: vi l = 0.6v, vih = 2.4v ? input rise and fall time: 5ns ? input and output timing reference level: 1.5v ? output load: see figures (including scope and jig) note 1. ambient temperature range depends on r/i-version. please see table on page 1. dq 1.5v r l = 500 ohm c l = 30 pf ( -5si, -5sr) c l = 100 pf ( -7si, -7sr)
r1lp0108e series r10ds0151ej0100 rev.1.00 page 8 of 12 2013.6.21 read cycle parameter symbol r1lp0108e**-5** r1lp0108e**-7** unit note min. max. min. max. read cycle time t rc 55 - 70 - ns address access time t aa - 55 - 70 ns chip select access time t acs1 - 55 - 70 ns t acs2 - 55 - 70 ns output enable to output valid t oe - 30 - 35 ns output hold from address change t oh 5 - 10 - ns chip select to output in low-z t clz1 5 - 10 - ns 2,3 t clz2 5 - 10 - ns 2,3 output enable to output in low-z t olz 5 - 5 - ns 2,3 chip deselect to output in high-z t chz1 0 20 0 25 ns 1,2,3 t chz2 0 20 0 25 ns 1,2,3 output disable to output in high-z t ohz 0 20 0 25 ns 1,2,3 write cycle parameter symbol r1lp0108e**-5** r1lp0108e**-7** unit note min. max. min. max. write cycle time t wc 55 - 70 - ns address valid to end of write t aw 50 - 55 - ns chip select to end of write t cw 50 - 55 - ns 5 write pulse width t wp 45 - 50 - ns 4 address setup time t as 0 - 0 - ns 6 write recovery time t wr 0 - 0 - ns 7 data to write time overlap t dw 25 - 30 - ns data hold from write time t dh 0 - 0 - ns output enable from end of write t ow 5 - 5 - ns 2 output disable to output in high-z t ohz 0 20 0 25 ns 1,2 write to output in high-z t whz 0 20 0 25 ns 1,2 note 1. t chz , t ohz and t whz are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. this parameter is sampled and not 100% tested. 3. at any given temperat ure and voltage condition, t hz max is less than t lz min both for a given device and from device to device. 4. a write occurs during the overlap of a low cs1#, a high cs2, a low we#. a write begins at the latest transition among cs1# going low, cs2 going high and we# going low. a write ends at the earliest transition among cs 1# going high, cs2 going low and we# going high. t wp is measured from the beginning of write to the end of write. 5. t cw is measured from the later of cs1# going low or cs2 going high to end of write. 6. t as is measured the address valid to the beginning of write. 7. t wr is measured from the earliest of cs1# or we# going high or cs2 going low to the end of write cycle. 8. don?t apply inverted phase signal ex ternally when dq pin is output mode.
r1lp0108e series r10ds0151ej0100 rev.1.00 page 9 of 12 2013.6.21 timing waveforms read cycle t aa cs1# a 0~16 t oh t clz1 t acs1 t oe t olz t chz1 oe# we# dq 0~7 v ih t ohz high impedance we# = ?h? level t rc valid data cs2 t clz2 t acs2 t chz2
r1lp0108e series r10ds0151ej0100 rev.1.00 page 10 of 12 2013.6.21 write cycle (1) (we# clock) cs1# t cw t ow t wc dq 0~7 t dw t dh valid data t ohz oe# we# t aw t as t wp t wr t whz t olz a 0~16 cs2 t cw
r1lp0108e series r10ds0151ej0100 rev.1.00 page 11 of 12 2013.6.21 write cycle (2) (cs1#, cs2 clock) cs1# a 0~16 t cw t wc t aw t as t wr oe# we# dq 0~7 v ih oe# = ?h? level t dw t dh t wp valid data cs2 t cw t wr t as
r1lp0108e series r10ds0151ej0100 rev.1.00 page 12 of 12 2013.6.21 low vcc data retention characteristics parameter symbol min. typ. max. unit test conditions *2 v cc for data retention v dr 2.0 - 5.5 v vin 0v (1) 0v cs2 0.2v or (2) cs1# vcc-0.2v, cs2 vcc-0.2v data retention current i ccdr - 0.6 *1 2 ? a ~+25c vcc=3.0v, vin 0v (1) 0v cs2 0.2v or (2) cs1# vcc-0.2v, cs2 vcc-0.2v - - 3 ? a ~+40c - - 8 ? a ~+70c - - 10 ? a ~+85c chip deselect time to data retention t cdr 0 - - ns see retention waveform. operation recovery time t r 5 - - ms note 1. typical parameter indicates the value for the center of distribution at 3.0v (t a= 25oc), and not 100% tested. 2. cs2 controls address buffer, we# buffer, cs1# bu ffer, oe# buffer and din buffer. if cs2 controls data retention mode, vin levels (address, we#, cs1#, oe#, dq) can be in the high impedance state. if cs1# controls data retent ion mode, cs2 must be cs2 vcc-0.2v or 0v cs2 0.2v. the other input levels (address, we# ,oe#, dq) can be in the high impedance state. low vcc data retention timing waveforms cs1# vcc (1) cs1# controlled t cdr t r 4.5v 4.5v 2.2v 2.2v v dr cs1# v cc - 0.2v cs2 vcc (2) cs2 controlled t cdr t r 4.5v 4.5v 0.2v 0.2v v dr 0v cs2 0.2v
all trademarks and registered trademarks are t he property of their respective owners. revision history r1lp0108e series data sheet rev. date description page summary 1.00 2013.6.21 - first edition issued
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